The testing procedure of print circuit board assembly (PCBA), an important step in the front-end processes is examining whether the pins on integrated circuits (ICs), connectors and other electronic devices are properly connected to the printed circuit board. Such test not only can increase product quality, it can also detect manufacturing defects in the front-end processes. Today, the “automatic optical inspection” method (AOI) has replaced the conventional manual inspections. The AOI method not only reduces cost and eliminates human errors, but it also increases the speed of inspection. However, AOI method can not be used to examine the pins, for example pins covered by the device itself such as in a “ball grid array” (BGA) packaged device. Such problem can be resolved by using an “automatic X-ray inspection” (AXI); however the cost for such inspection is high. The “in circuit tester” (ICT) provides another testing method. Under ICT, though it is required to fit different fixtures for different DUT, the probes on the fixture are capable of examining all the ICs on the printed circuit board assembly. Moreover, the fast testing speed, the accuracy of locating the defects, and a test coverage rate higher than both automatic optical inspection and automatic X-ray inspection, are all noted advantages of ICT.
A general ICT is equipped with a “manufacture defect analyzer” (MDA) to detect defects such as device damage, short, false welding and misplacement. However, MDA is only favorable for analog devices. A complete inspection of the digital circuits can be carried out by combining a “boundary-scan test” technique.
The Boundary-scan test is also known as JTAG test or IEEE1149.1. Such technique was proposed to IEEE committee by Join Test Action Group (JTAG) in 1988, and the standard of “Standard Test Access Port and Boundary-Scan Architecture” (IEEE std. 1149.1-1900) was established in 1990.
Connecting probes on the fixture to the testing point of DUT is the first step of conventional testing method. Once the probes are connected, the ICT generates signals to examine each DUT through the testing point. However, the complexity of printed circuit board assembly has increased significantly today, for example the number of pins is increased while the distance between the pins is decreased in devices such as CPU, ASIC, Chipset, etc. Such complexity change reduces the number of possible testing points. Boundary scan test provides a solution to the above mentioned problems. Today, circuits with boundary-scan function are commonly built in ICs for inspection purposes. Boundary-scan method scans through all the input and output pins of the integrated circuit devices in order to obtain the testing data of the said pins, or to examine whether the ICs and the printed circuit board are properly connected.
Referring to FIG. 1, it shows a block diagram of a conventional testing system arrangement, which includes an integrated circuit A (IC A) 10 and an integrated circuit B (IC B) 20, each contains a circuit with boundary-scan test function. Such a chip comprises four basic elements: Test Access Port (TAP) 30, TAP controller 40, Instruction Register (IR) and Data Register (DR), wherein only the TAP, TAP controller, IR, and some of the DRs are essential elements for operation. The required DRs are Boundary Scan Registers 50 and Bypass registers, while the other registers are optional. Next to the internal core-circuit, Boundary Scan Cells (BSCs) 55 are located between the internal core-circuit and the pins of ICs. BSCs serve as the probes inside the ICs; and serially connected BSCs form the Boundary Scan Register. During a test, at least four boundary-scan pins in TAP are used to control and convey the testing data through the TAP controller in IC. The four pins are: Test Data Output (TDO), Test Data Input (TDI), Test Clock (TCK), and Test Mode Select (TMS). A fifth pin, Test Reset (TRST), is optional. By inputting serial data to the TDI pin of IC A, which acts to send the test data to the BSCs, the test data can be shifted between BSCs. The test data can then be serially transferred from the TDO pin of IC A to the TDI pin of IC B, following a data shifting test in the BSCs of IC B. The shifted data can be observed at the TDO of IC B; a scan chain is herein completed. While the test data shifts to the output pin of BSCs in IC A, the internal connection within the chip and the interconnection between the chips of IC A and IC B carry out a parallel output to transfer the test data in BSCs to the bonding wires of a printed circuit board through the output pins. Meanwhile the test data is transferred to the input pins of IC B. Next, the BSCs of IC B first obtain the test data on the input pins by a parallel input and shift the data. Subsequently, the test data on output pins of IC B is compared to the test data on input pins of IC A; if the test data are the same, the connection between IC A and IC B, and the connections between some pins of IC A and some pins of IC B to the printed circuit B, are proper. On the contrary, the number of times data shifted indicates the number of improper connections between a pin of IC A and IC B. The boundary-scan test for a single IC can also be accomplished by alternating the serial and the parallel testing.
Boundary-scan test is capable of examining the internal function of IC and the pins connected to the printed circuit board. Boundary-scan test is a technique designed to overcome the difficulties in testing due to the improvement of IC manufacturing process. Except for reducing the number of probes on the fixture, tiny pins can also be examined easily by such a technique.
In order to examine the connection between the printed circuit board and the IC or the connector, Capacitive Coupling Test can be adopted as a convenient, reliable, and vector-less technique. Moreover, Capacitive Coupling Test does not damage the DUT since there is no destruction of DUT. Such method of examination uses an equivalent capacitance between the lead frame of IC and the extra sensor plate to establish a weak connection between the lead frame of IC and the extra sensor plate. The intensity of the coupled signals suggests the connecting condition between the electronic devices. By applying small AC signals to the testing pin of IC, the signals will couple to the sensor plate through the capacitance generated by the interface above and provide a reference voltage A if the printed circuit board is properly connected to the IC or the connector. On the contrary, if the printed circuit board is not properly connected to the IC, the value of capacitance at the interface will decrease and the signals cannot be coupled to the sensor plate easily, meanwhile a reference voltage B is provided. Whether an IC is properly connected to the printed circuit board can be determined by the difference of the small AC signals. Such a technique was first disclosed by Agilent Technologies in U.S. Pat. No. 5,254,953 in 1993, and it is now broadly adopted in the relevant industries.
As the manufacturing process for semiconductor improves, the printed circuit board assembly, for example the ball grid array (BGA) packaging, increases the density but lowers the volume of ICs at the same time, making it more difficult to reserve testing points on the DUT. The improvement of IC printed circuit board assembly suggests a significant growth in wire-density and a significant compression on board-space. Therefore, High Density Interconnect (HDI) technology is introduced to the manufacturing process of print circuit board to provide advantages of small size. By employing HDI technology, ICs or the connectors may be connected to the printed circuit board through its inner layers. As a result, the connections cannot be tested through the outside testing points as described above. Because the small AC signal cannot be delivered to the testing points of IC through outside probes, the inspection of the connectors that connect to the printed circuit board through its inner layers, such as PCI-E, DDR ⅔, CPU socket, becomes a great challenge.
Although other efforts have been developed in the probe-testing on the surface of high density printed circuit board, a proper testing method of delivering signals through the inner layer of printed circuit board to the DUT has not been achieved.
As a result, it is necessary to introduce a new technique to complement all the insufficiencies of prior arts. A testing system and method that overcomes the obstacles of signal delivery is required to increase the coverage of inspection and eliminate the blind spots of examination.